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Verification with UVM, Small group teaching
Small group teaching (English)
14.1.2021 – 2.5.2021
Active in period 3 (1.1.2021–7.3.2021)
Active in period 4 (8.3.2021–31.5.2021)
SystemVerilog and UVM are the current standards in SoC verification. On this course, you will implement a UVM environment for a simple subsystem.
Due to the remote teaching recommendation at the university, all teaching is remote. The remote teaching is facilitated in Zoom.
Study methods
Learning material
Learning environments
Required performances
Schedule information deleted
Schedule information deleted
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Method of attainment
Participation in teachingLanguage of instruction
EnglishResponsible organisation
Computing Sciences Studies
Persons responsible
Responsible teacher:
Arto Oinonen until 31.7.2024Primary course unit