Course unit, curriculum year 2026–2027
COMP.CE.240
Logic Synthesis, 5 cr
Tampere University
- Description
- Completion options
Teaching periods
Active in period 1 (1.8.2026–18.10.2026)
Active in period 2 (19.10.2026–31.12.2026)
Course code
COMP.CE.240Language of learning
EnglishAcademic years
2024–2025, 2025–2026, 2026–2027Level of study
Intermediate studiesGrading scale
General scale, 0-5Persons responsible
Responsible teacher:
Sakari LahtiResponsible organisation
Faculty of Information Technology and Communication Sciences 100 %
Coordinating organisation
Computing Sciences Studies 100 %
Content
Core content
- Main phases in implementing a digital circuit.
- Basics of VHDL language and how it is synthesized into circuit.
- Component verification and reuse. Principles of RTL simulators.
- Systems with multiple clock signals. Synchronization interfaces.
Complementary knowledge
- System realization in FPGA.
- Tri-state logic. Latches.
- Data sheets
Learning outcomes
Prerequisites
Compulsory prerequisites
Further information
Learning material
Equivalences
Studies that include this course
Completion option 1
Passed exam and accepted exercise work
All parts of the completion option are compulsory.
Exam
On-site self learning
12.10.2026 – 22.11.2026
Active in period 1 (1.8.2026–18.10.2026)
Active in period 2 (19.10.2026–31.12.2026)
Participation in teaching
Blended teaching
24.08.2026 – 22.10.2026
Active in period 1 (1.8.2026–18.10.2026)
Active in period 2 (19.10.2026–31.12.2026)