Course unit, curriculum year 2026–2027
COMP.CE.420
System-on-Chip Verification, 5 cr
Tampere University
- Description
- Completion options
Teaching periods
Active in period 1 (1.8.2026–18.10.2026)
Active in period 2 (19.10.2026–31.12.2026)
Active in period 3 (1.1.2027–7.3.2027)
Active in period 4 (8.3.2027–31.5.2027)
Course code
COMP.CE.420Language of learning
EnglishAcademic years
2024–2025, 2025–2026, 2026–2027Level of study
Advanced studiesGrading scale
General scale, 0-5Persons responsible
Responsible teacher:
Arto OinonenResponsible organisation
Faculty of Information Technology and Communication Sciences 100 %
Coordinating organisation
Computing Sciences Studies 100 %
Content
Core content
- Fundamental concepts in SoC verification
- Object-oriented properties of SystemVerilog language
- Universal Verification Methodology (UVM)
Complementary knowledge
- UVM on integration level
- Formal verification
Specialist knowledge
- UVM Register Abstraction Layer
- SystemVerilog DPI
Learning outcomes
Prerequisites
Recommended prerequisites
Further information
Learning material
Equivalences
Studies that include this course
Completion option 1
Grade 1 is given for students who complete the exercises with a defined number of points. Grades 2-5 can be achieved by taking the voluntary exam.
All parts of the completion option are compulsory.
Exam
28.09.2026 – 25.10.2026
Active in period 1 (1.8.2026–18.10.2026)
Active in period 2 (19.10.2026–31.12.2026)
Contact teaching
03.05.2027 – 30.05.2027
Active in period 4 (8.3.2027–31.5.2027)
Participation in teaching
Contact teaching
11.01.2027 – 31.05.2027
Active in period 3 (1.1.2027–7.3.2027)
Active in period 4 (8.3.2027–31.5.2027)
Open University completion options
The course is also available at the Open University